1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular a semiconductor device provided with a metal semiconductor field effect transistor (MOSFET) and a method of manufacturing the same.
2. Description of the Related Art
As a kind of MOSFET, a surrounding gate transistor (SGT) is known. To be more specific, this SGT is a MOSFET in which a source region, a gate region and a drain region are arranged vertically, and the gate electrode surrounds a silicon pillar (as disclosed in literature 1 (Takato, H, Sunouchi, K, et al., “Impact of Surrounding Gate Transistor (SGT) for ultra-high-density LSI's”, IEEE Transaction of Electron Devices, Vol. 38, No. 3, March 1991). Furthermore, a stacked-surrounding gate transistor (S-SGT) is known in which two or more SGTs are stacked together (as disclosed in literature 2 (T. Endoh et al., TOHOKU University, Sharp Corporation, “Novel Ultra High Density Flash Memory with A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM-2001).
In the case of forming such an S-SGT, in general, SGTs are successively formed downwards from the uppermost one. To be more specific, first, at an upper stage, a semiconductor pillar is formed, and an SGT is formed by using the semiconductor pillar; and then, at a subsequent stage, another semiconductor pillar which is larger in diameter than the above semiconductor pillar at the upper stage is formed, and another SGT is formed by using the other semiconductor pillar.
However, when an S-SGT is formed in the above manner, the diameters of semiconductor pillars for SGTs are different from each other such that the diameter of the upper one of any adjacent two of the semiconductor pillars is smaller than that of the other, that is, the diameter of the semiconductor pillar varies from one semiconductor pillar to another to gradually increase downwards. Inevitably, the place for providing the S-SGT is increased. Furthermore, since the diameters of the semiconductor pillars, which serve as channel regions, are different from each other as stated above, the SGTs respectively formed by using the semiconductor pillars have different characteristics.
Furthermore, it should be noted that in order that contact plugs be electrically connected to gate electrodes, a tiered structure of the S-SGT in which the SGTs are arranged in a stepwise manner is utilized, i.e., the steps of the S-SGT are utilized. Thus, as the number of the SGTs increases, the area of the place for providing the formed S-SGT increases. On the other hand, in a single SGT, after a gate electrode is formed, it is extended (that is, a conductive layer is added which is electrically connected to the gate electrode), and a contact plug is then formed. In this case, when the conductive layer is formed, the following positioning error easily occurs: for example, the conductive layer is not connected to the gate electrode, or it is formed in the semiconductor pillar. Therefore, a contact plug cannot be formed.